The present invention relates to logic circuits and, more particularly, to logic signal multiplier circuits having low power consumption.
In small volume portable devices, such as watches, pocket calculators, hearing aids, etc., employing electronic circuits, most such electronic circuits are supplied from batteries or cells providing a supply voltage having standardized voltages of 1.5 volts, or in the case of lithium cells, 3 volts. In such devices, certain techniques (including particular CMOS techniques) have been developed to insure correct operation of the electronic circuits at such relatively low voltages. Nevertheless, there are still applications in which it is necessary to obtain higher voltages from the electronic circuits than are provided by the supply voltage.
In a known example involving the control of display devices (including liquid crystal displays or stepping motors) such problems have been resolved in one instance by the use of diode voltage multipliers, as described in Swiss Pat. No. 621917. In another instance, the problem has been addressed by the use of a multiplier similar to the aforementioned Swiss patent in which the diodes are replaced by MOS transistors, as described in Swiss Pat. No. 593510. In such instances, however, this type of multiplier has low power efficiency which limits its application to the control of relatively slow circuits.
The ability to provide voltage multipliers is also particularly important in the field relating to switched capacitor circuits. In such circuits, capacitors, amplifiers and switches are used to insure the transfer of charges between the capacitors in accordance with predetermined sequences. Such circuits are described in an article entitled "Microwatt Switched Capacitor Circuit Design" by E. Vittoz, in Electro Component Science and Technology, Volume 9, No. 4, 1982, pp. 263-273. As previously indicated, one of the basic elements of such circuits is the switch, which is implemented using MOS transistors. Such transistors are usually controlled by signals that have values which do not exceed the value of the supply voltages. In a p- or n-channel MOS transistor, such limitation imposed by the supply voltage on the control signal prevents the assurance of total conduction for all values of voltage applied to the drain of such a transistor. As a result, a transmission gate, formed by placing a p-channel MOS transistor and an n-channel MOS transistor in parallel and controlled by opposite phase signals, is often employed to reduce the disadvantages noted above. However, such an implementation requires the use of two transistors and two control signals per switch, thereby requiring the employment of significant circuit area when large numbers of switches are involved.
Accordingly, the present invention has been developed to provide a logic signal multiplier circuit which overcomes the disadvantages of the above-known and similar techniques.